Flash memory device having single page buffer structure

ABSTRACT

A flash memory device includes memory cells, a common node, a sense node connected to a selected bit line, a first register connected to the common node, a second register connected to the common node and the sense node, a common sense circuit connected to the common node, the sense node, and a control node; a switch, and a pre-charge circuit connected to the control node and configured to pre-charge the control node.

BACKGROUND

1. Field of the Invention

The present invention is related to a semiconductor memory device. In particular, the present invention is related to a non-volatile semiconductor memory device capable of storing multi-bit data.

This application claims priority to Korean Patent Application No. 2005-69127, filed Jul. 28, 2005, the subject matter of which is hereby incorporated by reference in its entirety.

2. Description of the Related Art

Semiconductor memory devices are vital components in the design of digital logic systems such as computers, and substantially enable microprocessor-based applications ranging from satellites to consumer electronics. Therefore, advances in the fabrication of semiconductor memory devices, including process enhancements and technological developments achieved through scaling for higher integration density and faster operational speeds, help establish performance standards for other digital logic families. A semiconductor memory device may be a volatile random access memory (RAMs) device or a non-volatile memory device. In RAM, logic information is stored either by setting up the logic state of a bi-stable flip-flop, as in a static random access memory (SRAM), or through charging a capacitor, as in a dynamic random access memory (DRAM). In both SRAMs and DRAMs, the stored data may be read from memory as long as power is supplied to the device, but the stored data is lost when power is not supplied. Hence, SRAMs and DRAMs are called volatile semiconductor memory devices.

Non-volatile semiconductor devices, such as MROMs, PROMs, EPROMs, and EEPROMs, are capable of storing data even when power is not supplied to the device. Depending upon the fabrication technology used, a non-volatile semiconductor device may or may not be reprogrammable (i.e., data storage in the device may be changeable or permanent). Non-volatile semiconductor devices are used for program and microcode storage in a wide variety of applications, such as those common to the computer, avionics, telecommunications, and consumer electronics industries.

A combination of volatile and non-volatile memory storage is available in single chip devices, such as non-volatile SRAM (nvRAM). Such devices are used in systems that require fast, programmable non-volatile memory. In addition, dozens of special memory architectures containing additional logic circuitry adapted to optimize memory device performance for application-specific tasks have been created.

As compared with other types of memory devices, it is relatively difficult to write data to, or erase data from non-volatile semiconductor devices, such as the MROM, PROM, and EPROM. On the other hand, EEPROM devices may be electrically erased or written. As a result, the use of EEPROM devices has been expanded and to auxiliary memories or system programming devices requiring continuous update. In particular, a flash EEPROM (hereinafter referred to as “a flash memory device”) has a higher degree of integration than a conventional EEPROM device, so it is preferable to use a flash memory device in a large auxiliary memory as opposed to a conventional EEPROM device. Also, a NAND-type flash memory device (i.e., a flash memory device comprising NAND-type flash memory) has a higher degree of integration than a well-known, NOR-type flash memory device (i.e., a flash memory device comprising NOR-type flash memory).

A NAND-type flash memory device comprises a memory cell array in which digital information is stored, and the memory cell array comprises a plurality of cell strings (called NAND strings). The flash memory device also comprises a page buffer circuit that stores data in the memory cell array and reads data from the memory cell array. As is well known in the art, memory cells of a NAND-type flash memory device are erased and programmed using Flowler-Nordheim tunneling current. Erase and program methods for NAND-type flash memory devices are disclosed, for example, in U.S. Pat. Nos. 5,473,563 and 5,696,717, the subject matter of which is hereby incorporated by reference in its entirety.

Figure (FIG.) 1 is a block diagram showing a conventional flash memory device. As illustrated in FIG. 1, a flash memory device 10 comprises a memory cell array 12, a row decoder circuit 14, and a page buffer circuit 16. Memory cell array 12 comprises memory cells arranged along rows (i.e., along word lines) and along columns (i.e., along columns that correspond to bit lines). The memory cells are configured in a NAND string structure. The word lines (i.e., the rows) of memory cell array 12 are driven by row decoder circuit 14, and the bit lines (i.e., the columns) are driven by page buffer circuit 16. Each memory cell stores 1-bit data or multi-bit data (e.g., 2-bit data). A page buffer circuit configured to store 2-bit data in each memory cell must be designed differently from a page buffer circuit configured to store 1-bit data in each memory cell. As is well known in the art, 1-bit data is stored in a memory cell by a page buffer circuit comprising one latch, while 2-bit data is stored in a memory cell by a page buffer circuit comprising two latches.

Exemplary page buffer circuits that store 2-bit data in memory cells are disclosed, for example, in U.S. Pat. Nos. 5,768,188; 5,862,974; 5,966,326; and, 5,982,663, the subject matter of which is hereby incorporated by reference in its entirety.

In each of the references mentioned above, the disclosed page buffer circuit comprises two latches and requires sense circuits to transfer data stored in memory cells to respective latches during a read operation. Since sense paths to the respective latches differ, a mismatch between sense margins may arise. In particular, in a flash memory device that stores multi-bit data, read errors are caused by the mismatch of sense margins.

With continuing demand for a higher integration density, flash memory devices are increasingly required to perform various operations, such as cache program, page copy-back, etc. In the cache program operation, while data is programmed during the current program interval, data to be programmed during the next program interval is loaded into a page buffer circuit. In the page copy-back operation, data is moved from one page to another through a page buffer circuit. Like a multi-bit flash memory device, a page buffer circuit requires two latches to perform these operations.

Exemplary page buffer circuits adapted to perform the above-mentioned operations are disclosed, for example, U.S. Pat. Nos. 6,717,857 and 6,671,204, the subject matter of which is hereby incorporated by reference in its entirety.

Unfortunately, a conventional page buffer circuit capable of performing the page copy-back and/or cache program operations has a different structure than a conventional page buffer circuit capable of performing multi-bit programming. Thus, separate page buffer circuits must be provided to perform all of these disparate operations. Unfortunately, the provision of multiple page buffer circuits having different structures drives the cost of memory devices higher.

SUMMARY OF THE INVENTION

Embodiments of the invention provide a flash memory device capable of performing multi-bit program and read operations, single bit program and read operations, a cache program operation, and/or a page copy-back operation using a single page buffer structure.

In one embodiment, the invention provides a flash memory device comprising a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines, a common node, a sense node connected to a selected bit line, a first register connected to the common node, and a second register connected to the common node and the sense node. The flash memory device further comprises a common sense circuit that is connected to the common node, the sense node, and a control node and is configured to selectively provide a first voltage to the common node in accordance with a voltage level of the sense node and a voltage level of the control node; a switch configured to provide a second voltage to the control node, wherein the second voltage corresponds to the data value stored in the first register; and a pre-charge circuit connected to the control node and configured to pre-charge the control node.

In another embodiment, the invention provides a flash memory device comprising an array of memory cells arranged along a plurality word lines and a plurality of bit lines, a bit line select and bias block configured to select a group of bit lines comprising at least one bit line of the pluralities of bit lines, and a page buffer block comprising a plurality of page buffers, each of which corresponds to at least one bit line of the plurality of bit lines. Each of the page buffers comprises a common node, a sense node connected to a selected bit line, a first register connected to the common node, and a second register connected to the common node and the sense node.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention will be described hereinafter with reference to the accompanying drawings, in which like reference symbols indicate the same or similar components. In the drawings:

FIG. 1 is a block diagram showing a conventional flash memory device;

FIG. 2 is a block diagram of a flash memory device in accordance with the present invention;

FIG. 3 is a circuit diagram of the page buffer illustrated in FIG. 2;

FIGS. 4A and 4B are diagrams illustrating a multi-bit program operation in accordance with the present invention;

FIG. 5 is a flowchart describing an LSB program operation of a flash memory device in accordance with the present invention;

FIG. 6 is a circuit diagram illustrating the flow of data through portions of a flash memory device in accordance with the present invention during the LSB program operation;

FIG. 7 is a flowchart describing an MSB program operation of a flash memory device in accordance with the present invention;

FIGS. 8A and 8B are circuit diagrams illustrating the flow of data through portions of a flash memory device in accordance with the present invention during the MSB program operation;

FIG. 9A is a circuit diagram illustrating the flow of data through portions of a flash memory device in accordance with the present invention during an MSB read operation;

FIG. 9B shows a read voltage applied to the selected word line during an MSB read operation;

FIG. 10A is a circuit diagram illustrating the flow of data through portions of a flash memory device in accordance with the present invention during an LSB read operation;

FIG. 10B shows read voltages applied to the selected word line during an LSB read operation;

FIG. 11 is a circuit diagram illustrating the flow of data through portions of a flash memory device in accordance with the present invention during a cache program operation;

FIG. 12A is a diagram illustrating a page copy-back operation of a flash memory device in accordance with the present invention;

FIG. 12B is a circuit diagram illustrating the flow of data through portions of a flash memory device in accordance with the present invention during the page copy-back operation of FIG. 12A;

FIG. 12C is a circuit diagram illustrating an alternative flow of data through portions of a flash memory device in accordance with the present invention during the page copy-back operation of FIG. 12A;

FIG. 13A is a diagram illustrating a page copy-back operation in accordance with the present invention; and,

FIG. 13B illustrates the flow of data through portions of a flash memory device in accordance with the present invention during the page copy-back operation of FIG. 13A.

DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

FIG. 2 is a block diagram of a flash memory device in accordance with one embodiment of the invention. Referring to FIG. 2, a flash memory device 1000 comprises a memory cell array 100 adapted to store data. Memory cell array 100 comprises a plurality of memory cells arranged in rows and columns (i.e., arranged along a plurality of word lines and a plurality of bit lines). Each of the memory cells stores 1-bit data or multi-bit data (e.g., 2-bit data). A row decoder circuit 200 is adapted to select a row of memory cell array 100, drive the selected row with a first word line voltage, and drive each of the unselected rows with a second word line voltage. For example, during a first program operation, row decoder circuit 200 drives a selected row with a program voltage and unselected rows with a pass voltage, respectively. Also, for example, during a read operation, row decoder circuit 200 drives a selected row with a read voltage and unselected rows with a pass voltage, respectively. Examples of read operations are verify read operations of multi-bit and single bit operating modes, normal read operations, and the like.

Flash memory device 1000 further comprises; a bit line select and bias block 300, a page buffer block 400, a control logic block 500, and a page buffer decoder circuit 600.

Control logic block 500 controls bit line select and bias block 300. Bit line select and bias block 300 is adapted to select a group of bit lines from among the plurality of bit lines of memory cell array 100. For example, during program and read operations, bit line select and bias block 300 is adapted to select either odd-numbered bit lines BLo or even-numbered bit lines BLe from among the plurality of bit lines. Thus, each row comprises two pages. Bit line select and bias block 300 comprises a plurality of bit line select and bias circuits 300 a through 300 b, each of which corresponds to two bit lines. Also, the bit lines of a given bit line select and bias circuit (e.g., 300 a) correspond to different pages, respectively, within a given row (i.e., word line). During a given operation, each of the bit line select and bias circuits 300 a through 300 b performs the operation on one of bit lines BLe or BLo. As described above, one row comprises two pages, but it will be clear to one skilled in the art that one row may comprise one page or more than two pages. Various conventionally understood bit line select and bias block 300 circuits may be incorporated into the working example. (See, for example, U.S. Pat. Nos. 6,717,857 and 6,671,204). Therefore, a detailed description of this block will not be given herein.

Page buffer block 400 operates as a sense amplifier or a write driver in accordance with the operating mode of flash memory device 1000. For example, during a program operating mode (i.e., during a first program operation), page buffer block 400 stores data input through page buffer decoder circuit 600 and drives bit lines selected by bit line select and bias block 300 with a program voltage (e.g., a ground voltage) or a program-inhibition voltage (e.g., a power supply voltage) in accordance with the data stored in page buffer block 400. During a read operating mode (i.e., during a read operation), page buffer block 400 senses data from a selected memory cell through a selected bit line (i.e., a bit line that corresponds to the selected memory cell). The sensed data is output to a data line bus (or to a component outside of flash memory device 1000). Control logic block 500 controls page buffer block 400. Page buffer block 400 comprises a plurality of page buffers 400 a through 400 b, each of which corresponds to a respective bit line select and bias circuits 300 a through 300 b of bit line select and bias block 300. Since page buffers 400 a through 400 b are each configured in the same way, the constituent elements of each of page buffers 400 a through 400 b will be described in more detail below in relation to only one exemplary page buffer (e.g., 400 a).

Page buffer 400 a comprises two registers 410 and 420, a load circuit 430, a common sense circuit 440, a data output circuit 450, a pre-charge circuit 460, and a switch 470. Register 410 is called a cache register and register 420 is called a main register. A sense node S0 is electrically connected to a bit line selected by a corresponding bit line select and bias circuit 300 a. Registers 410 and 420 are configured to store data, as will be described in more detail below. Load circuit 430 is electrically connected to sense node S0 and supplies a current to sense node S0. Data output circuit 450 is configured to output data stored in main register 420 to page buffer decoder circuit 600.

Still referring to FIG. 2, pre-charge circuit 460 is configured to pre-charge a control node CN to a logic high level during the sense interval of each read operation. The sense interval is an interval during which a voltage apparent on a selected bit line and sense node S0 is provided to common node CSN. Common sense circuit 440 is connected to sense node S0 and control node CN and is configured to selectively provide a voltage to common node CN in accordance with the voltage level of sense node S0. Switch 470 is configured to transfer data stored in register 410 to control node CN (or common sense circuit 440). In particular, switch 470 transfers the data stored in register 410 to the common sense circuit 440 during a “00” verify read interval of a multi-bit program operation. At this time, pre-charge circuit 460 is disabled, as will be described in more detail below.

The present flash memory device can perform multi-bit program, cache program, and page copy-back functions using the page buffer structure described above. That is, it is possible to carry out a multi-bit program operation, a cache program operation, and a page copy-back operation using a single page buffer structure. Thus, when using a device that comprises a page buffer having the structure described above, it is not necessary to manage separate memory devices to support the different functions mentioned above.

FIG. 3 is a circuit diagram of page buffer 400 a of FIG. 2. As shown in FIG. 3, page buffer 400 a comprises two registers 410 and 420, load circuit 430, common sense circuit 440, data output circuit 450, pre-charge circuit 460, and switch 470.

Cache register 410 has four NMOS transistors 411, 412, 413, and 416; and two inverters 414 and 415. Inverters 414 and 415 are connected to form a latch 417. Cache register 410 comprises a register switch circuit comprising NMOS transistors 411, 412, and 413. NMOS transistor 411 has a source, a drain connected to a first latch node N1, and a gate connected to a control signal C1. NMOS transistor 413 is connected between the source of NMOS transistor 411 and a ground voltage, and the gate of NMOS transistor 413 is connected to a control signal C3. NMOS transistor 412 has a gate connected to a control signal C2, a drain connected to a second latch node N2, and a source connected to the drain of NMOS transistor 413. NMOS transistor 416 is connected between second latch node N2 and common node CSN, and the gate of NMOS transistor 416 is connected to a control signal C4 (i.e., an initial read control signal).

In this exemplary embodiment, control signals C1 and C2 have complementary logic levels during the data load interval, which is when latch 417 receives program data. For example, when the data value “1” is loaded into cache register 410, control signal C1 has a logic high level and control signal C2 has a logic low level. When the data value of “0” is loaded into cache register 410, control signal C1 has a logic low level and control signal C2 has a logic high level. In order to reset latch 417, control signals C1 and C2 are set to a logic high level and a logic low level, and control signal C3 is set to a logic high level. Control logic block 500 of FIG. 2 provides control signal C3 to page buffer 400 a, and control signal C3 is activated (i.e., set to a logic high level) during the data load interval. Control signal C4 is activated during the initial read interval of the multi-bit program operation. NMOS transistors 411, 412 and 413 constitute a register switch circuit that selectively connects latch nodes N1 and N2 to a ground voltage in response to control signals C1, C2 and C3. As used herein, “program data” is a representative data value that corresponds to an actual data value that will be programmed into a selected memory cell. In one embodiment, program data may be LSB program data (i.e., program data that represents an actual data value to be programmed into a selected memory cell during an LSB program operation), or MSB program data (i.e., program data that represents an actual data value to be programmed into a selected memory cell during an MSB program operation). Also, as used herein, when a data value is said to be “loaded into,” “loaded in,” “stored in,” etc., a latch (e.g., latch 416), it means that logic levels are stored in the latch nodes of the latch (e.g., first and second latch nodes N1 and N2) in a way that represents the data value to be stored (or loaded, etc.) in the latch. Also, as used herein, the term “activate” as used in reference to a signal means to set the signal to a logically high level. Similarly, the term “deactivate” means setting a signal to a logically low level. (In this regard, however, low and high are merely selected logic examples and could be easily reversed in their nature).

Continuing to refer to FIG. 3, main register 420 has four NMOS transistors 421, 422, 423, and 426; and two inverters 424 and 425. Inverters 424 and 425 are connected to form a latch 427. NMOS transistor 421 has a gate connected to a control signal C5, a drain connected to a third latch node N3, and a source connected to common node CSN. NMOS transistor 422 has a gate connected to a control signal C6, a drain connected to a fourth latch node N4, and a source connected to common node CSN. NMOS transistor 423 has a gate connected to a control signal C7, a drain connected to common node CSN, and a source connected to a ground voltage. NMOS transistor 426 has a gate that is connected to a control signal C8, and NMOS transistor 426 is connected between sense node S0 and latch node N4.

In this exemplary embodiment, control logic block 500 of FIG. 2 provides control signals C5, C6, C7, and C8 to page buffer 400 a. Control signal C6 is activated when data stored in cache register 410 is transferred through common sense circuit 440 to main register 420. Control signal C5 is activated while latch 427 is being reset and during the sense interval of each read operation. Control signal C7 is activated while latch 427 is being reset and during each data output interval. Control signal C8 is activated when data stored in latch 427 is transferred to a bit line during a program interval.

Load circuit 430 comprises a PMOS transistor 431 that is connected between a power supply voltage and sense node S0 and is controlled in accordance with a control signal C9 (i.e., the gate of PMOS transistor 431 is connected to control signal C9). Common sense circuit 440 comprises three NMOS transistors 441, 442 and 443. NMOS transistor 441 has a source, a drain connected to common node CSN, and a gate connected to control node CN. NMOS transistor 442 has a gate connected to sense node S0, a source connected to a ground voltage, and a drain connected to the source of NMOS transistor 441. NMOS transistor 443 has a gate connected to a control signal C10, which functions as a data dump control signal, a drain connected to the source of NMOS transistor 441, and a source connected to a ground voltage. Data output circuit 450 has two NMOS transistors 451 and 452 that are connected in series between a signal line DOL and a ground voltage. NMOS transistor 451 is controlled in accordance with the logic level of latch node N3 of main register 420, and NMOS transistor 452 is controlled in accordance with control signal C7.

Pre-charge circuit 460 comprises a PMOS transistor 461 that is connected between a power supply voltage and control node CN, and is controlled in accordance with a control signal C11 (i.e., a latch control signal). Switch 470 comprises a PMOS transistor 471 and an NMOS transistor 472. PMOS and NMOS transistors 471 and 472 are connected in parallel between latch node N1 of cache register 410 and control node CN (i.e., the gate of NMOS transistor 441). NMOS transistor 472 is controlled in accordance with control signal C11, and PMOS transistor 471 is controlled in accordance with an inverted version of control signal nC11. When pre-charge circuit 460 operates, switch 470 does not, and when pre-charge circuit 460 does not operate, switch 470 does.

In this exemplary embodiment, control signal C11 is activated during the “01” verify read interval and the initial read interval of a MSB program operation, and during the sense interval of a normal read operation. In addition, control signal C11 maintains a logic low level during the “00” verify read interval of the MSB program operation.

A multi-bit program operation for the flash memory device of the present invention will now be described generally.

To store 2-bit data in a selected memory cell, a flash memory device in accordance with the present invention performs both an LSB program operation and an MSB program operation. Through the LSB and MSB program operations, a selected memory cell is programmed to store one of the following data values: “11,” “10,” , “00,” or “01.” A memory cell storing a data value of “11” is an erased memory cell, and a memory cell storing a data value of “10” has a threshold voltage higher than that of a memory cell storing a data value of “11. ” In addition, a memory cell storing a data value of “00” has a threshold voltage higher than that of a memory cell storing a data value of “10.” Finally, a memory cell storing a data value of “01” has a threshold voltage higher than that of a memory cell storing a data value of “00.” Under the conditions set forth above, after an LSB program operation has been performed on a selected memory cell, the selected memory cell stores a data value of either “11” (i.e., the selected memory cell is an erased memory cell), or “10,” as illustrated in FIG. 4A. After performing the MSB program operation, which is performed after the LSB program operation, a selected memory cell that stored a data value of “11” after the LSB program operation will store a data value of either “11” or “01,” while a selected memory cell that stored a data value of “10” after the LSB program operation will store a data value of “10” or “00,” as illustrated in FIG. 4B.

FIG. 5 is a flowchart describing an LSB program operation for a flash memory device in accordance with the present invention, and FIG. 6 is a circuit diagram illustrating the flow of data through portions of a flash memory device in accordance with the present invention during the LSB program operation. An LSB program operation will now be described with reference to FIGS. 3, 4A, 5, and 6. An LSB program operation is performed through an iteration of program loops. Each program loop comprises an LSB program interval that comprises a first program operation and an LSB verify interval that comprises an LSB verify read operation. The LSB verify read operation is called a “10” verify read operation.

Once the LSB program operation commences, first latch node N1 and second latch node N2 of cache register 410 are reset to a logic low level and a logic high level, respectively (S100). The reset operation is performed on cache register 410 by activating control signals C1 and C3. After resetting cache register 410, LSB program data is loaded into cache register 410 through page buffer decoder circuit 600 (S120). During a data load interval, LSB program data having a value of either “1” or “0” may be loaded into cache register 410, and in either case control signal C3 is set to a logic high level. LSB program data having a value of “1” is loaded into cache register 410 by setting control signal C1 to a logic high level and setting control signal C2 to a logic low level. Thus, first latch node N1 is grounded through NMOS transistors 411 and 413 (i.e., through signal path {circle around (1)} of FIG. 6), which sets first latch node N1 to a logic low level and second latch node N2 to a logic high level. On the other hand, LSB program data having a value of “0” is loaded into cache register 410 by setting control signal C1 to a logic low level and setting control signal C2 to a logic high level. Thus, second latch node N2 is grounded through NMOS transistors 412 and 413, and as a result first latch node N1 is set to a logic high level and second latch node N2 is set to a logic low level.

After LSB program data is loaded into cache register 410, main register 420 is reset such that latch nodes N3 and N4 have a logic low level and a logic high level, respectively (S140). The reset operation is performed on main register 420 by activating control signals C5 and C7. After resetting main register 420, the data stored in cache register 410 is transferred to main register 420 through switch 470 and common sense circuit 440 by activating control signals C6, C10, and C11 (S160). When control signal C11 is set to a logic high level, PMOS transistor 461 of pre-charge circuit 460 is turned (or remains) off and NMOS transistor 441 is selectively turned on in accordance with the data stored in cache register 410. The activated control signal C10 turns on NMOS transistor 443. When LSB program data having a value of “1” was previously loaded into cache register 410, latch node N1 was set to a logic low level, so latch node N3 of main register 420 maintains the logic low level at which it was set when main register 420 was reset. That is, NMOS transistor 441 is turned (or remains) off because latch node N1 has a logic low level; and thus, a current path {circle around (3)} of FIG. 6 is not formed between common node CSN and a ground voltage. Thus, third latch node N3 maintains its logic low level and fourth latch node N4 maintains its logic high level (i.e., main register 420 maintains the state it was in after the reset operation). On the other hand, when LSB program data having a value of “0” was previously loaded into cache register 410, latch node N1 was set to a logic high level; and thus, NMOS transistor 441 will be turned on (see signal path {circle around (2)} of FIG. 6). So, latch node N4 of main register 420 is grounded through NMOS transistors 422, 441, and 443 (i.e., through a signal path {circle around (3)} of FIG. 6). Thus, latch nodes N3 and N4 of main register 420 are set to a logic high level and a logic low level, respectively. As used herein, storing a data value in a sense and register circuit, memory cell, or any other component of a flash memory device may refer to either changing the data value that is stored in that component or leaving the data value stored in that component unchanged.

Once the LSB program data has been transferred from cache register 410 to main register 420 as described above, a first program operation is executed (S180). When the first program operation is executed, the voltage level of the selected bit line is determined through a signal path {circle around (4)} of FIG. 6 in accordance with the data stored in main register 420. The first program operation is well known in the art, so description thereof is omitted here. After the first program operation is performed, an operation is performed to determine whether or not the selected memory cell has been programmed successfully (S190). That is, an LSB verify read operation (i.e., the “10” verify read operation) is performed. During the “10” verify read operation, a verify voltage Vvfy1 (refer to FIG. 4A) applied to the selected word line (i.e., the word line that corresponds to the selected memory cell) and a resulting voltage variation of the selected bit line is reflected on sense node S0 through signal path {circle around (5)} of FIG. 6. For example, if the selected memory cell has a threshold voltage lower than verify voltage Vvfy1, the voltage level of sense node S0 (in accordance with the voltage level of the selected bit line) decreases toward a ground voltage. When this occurs, the low voltage of sense node S0 turns off NMOS transistor 442 of common sense circuit 440. During the “10” verify read operation, control signal C5 is set to a logic high level, control signal C11 is set to a logic low level, and control signal C10 is set to (or remains at) a logic low level. Thus, although NMOS transistors 421 and 441 are turned on, the data value stored in main register 420 does not change. On the other hand, if the selected memory cell has a threshold greater than or equal to verify voltage Vvfy1, the voltage level of sense node S0 (in accordance with the voltage level of the selected bit line) increases toward a power supply voltage. When this occurs, the high voltage level of sense node S0 turns on NMOS transistor 442 of common sense circuit 440. During the “10” verify read operation, since NMOS transistors 421, 441 and 442 are turned on, signal path {circle around (6)} of FIG. 6 is formed. Thus, latch nodes N3 and N4 are set to a logic low level and a logic high level, respectively. When latch node N4 is set to a logic high level, a memory cell is program inhibited during any subsequently executed LSB program loops.

After the “10” verify read operation is executed, the data stored in main register 420 is transferred to page buffer decoder circuit 600 through data output circuit 450 by activating control signal C7. For example, when latch node N3 has a logic low level, NMOS transistor 451 of data output circuit 450 is turned off; and thus, signal line DOL is maintains its pre-charged state (e.g., a logic high level). On the other hand, when latch node N3 has a logic high level, NMOS transistor 451 is turned on; and thus, signal line DOL is grounded (see signal path {circle around (7)} of FIG. 6). The logic state of signal line DOL is provided to a pass/fail check circuit (not shown) through page buffer decoder circuit 600. The pass/fail check circuit determines, based on the data input to the pass/fail check circuit, whether the selected memory cell has been successfully programmed. In accordance with the judgment result, another LSB program loop is executed or the LSB program operation ends.

FIG. 7 is a flowchart describing an MSB program operation of a flash memory device in accordance with the present invention, and FIGS. 8A and 8B are circuit diagrams illustrating the flow of data through portions of a flash memory device in accordance with the present invention during the MSB program operation. An MSB program operation will now be described with reference to FIGS. 3, 4B, 7, 8A, and 8B. An MSB program operation is performed through the iteration of MSB program loops. Each MSB program loop comprises an MSB program interval that comprises a first program operation, a first MSB verify read interval that comprises a first MSB verify read operation, and a second MSB verify read interval that comprises a second MSB verify read operation. The first MSB verify read operation is called a “00” verify read operation and the second MSB verify read operation is called a “01” verify read operation. As will be described below, the first and second MSB verify read operations are executed sequentially.

In FIG. 7, steps S200 through S260 of the MSB program operation are the same as steps S100 through S160 of the LSB program operation, respectively, except that in steps S220 and S260, MSB program data is manipulated rather than LSB program data as in steps S120 and S160. Thus, further description of steps S200 through S260 is omitted here. Once the MSB program data loaded in cache register 410 is transferred to main register 420 through switch circuit 460 (S260), a read operation, which will be referred to hereinafter as an initial read operation, is executed. During the initial read operation, a first data value that corresponds to the LSB data value that was programmed into the selected memory cell during the LSB program operation is stored in cache register 410 (S280).

During the initial read operation, latch 417 of cache register 410 is reset. That is, latch 417 is reset such that latch nodes N1 and N2 are set to a logic low level and a logic high level, respectively. Then, a read voltage (e.g., a voltage between the threshold voltage distribution for the data value “11” and the threshold voltage distribution for the data value “10”) is applied to the selected word line and the resulting voltage variation of the selected bit line is reflected on sense node S0 through signal path {circle around (4)} of FIG. 8A. For example, when the threshold voltage of the selected memory cell is lower than the read voltage (i.e., when the selected memory cell has data value of “11,” which is the erased state), the voltage level of sense node S0 decreases toward a ground voltage. As a result, NMOS transistor 442 of sense circuit 440 is turned (or remains) off. That is, signal path {circle around (5)} of FIG. 8A is not formed. During the initial read operation, control signal C4 is set to a logic high level, control signal C11 is set to a logic low level, and control signal C10 is set to (or remains at) a logic low level. Although NMOS transistors 461 and 441 are turned on, the data value stored in cache register 410 is not changed. On the other hand, when the threshold voltage of the selected memory cell is greater than or equal to the read voltage (i.e., when the selected memory cell has a data value of “10”), the voltage level of sense node S0 increases to a power supply voltage, thus turning on NMOS transistor 442 of common sense circuit 440. Since NMOS transistors 461 and 441 are turned on during the initial read operation, signal path {circle around (5)} of FIG. 8A is formed. Thus, latch nodes N1 and N2 are set to a logic high level and a logic low level, respectively.

Once the initial read operation is completed, the selected memory cell is programmed in accordance with the MSB program data (S300), which has been stored in main register 420 through steps S200 through S260. When the first program operation is carried out, the voltage of the selected bit line is determined through signal path {circle around (6)} of FIG. 8A in accordance with the data stored in main register 420. The first program operation is well known in the art, so a description thereof is omitted here. After the first program operation is performed, an operation is performed to determine whether or not the selected memory cell has been programmed successfully (S320). As set forth above, each MSB program loop comprises a program operation and “00” and “01” verify read operations. The “00” verify read operation determines whether a selected memory cell was programmed from storing a data value of “10” to storing a data value of “00.” The “01” verify read operation determines whether a selected memory cell was programmed from storing a data value of “11” to storing a data value of “01.” The “00” and “01” verify read operations will be described in more detail below.

Referring to FIG. 8B, during the “00” verify read operation, a verify voltage Vvfy2 (see FIG. 4A) is applied to the selected word line and the resulting voltage level variation of the selected bit line is reflected on sense node S0 through signal path {circle around (7)} of FIG. 8B. Control signals C5 and C11 are set to a logic high level during the “00” verify read operation. Under the conditions set forth above, common node CSN is selectively grounded through common sense circuit 440 in accordance with the data stored in cache register 410. In particular, since control signal C11 has a logic high level during the “00” verify read operation, PMOS transistor 461 is turned off and switch 470 is activated. During the “00” verify read operation, NMOS transistor 441 of common sense circuit 440 is selectively turned on in accordance with the data stored in cache register 410. As described above, if, during the LSB program operation, the selected memory cell was programmed to store the data value “11” (i.e., maintain an erased state), latch nodes N1 and N2 of cache register 410 are set to a logic low level and a logic high level, respectively. On the other hand, if, during the LSB program operation, the selected memory cell was programmed to store the data value “10,” latch nodes N1 and N2 of cache register 410 are set to a logic high level and a logic low level, respectively.

If the memory cell that is to be programmed during the MSB program operation (i.e., the selected memory cell) stores the data value “11” (i.e., has an erased state) after the LSB program operation, NMOS transistor 441 of common sense circuit 440 is turned off in accordance with the data that was stored in cache register 410 during the initial read operation. Accordingly, signal path {circle around (9)} of FIG. 8B is not formed. Thus, the data value stored in main register 420 is not changed. Afterwards, in accordance with the data stored in main register 420, the selected memory cell will continue of store the data value “11,” or will be programmed to store a data value of “01.” On the other hand, if the memory cell that is to be programmed during the MSB program operation (i.e., the selected memory cell) stored the data value “10” after the LSB program operation, NMOS transistor 441 is turned on in accordance with the data that was stored in cache register 410 during the initial read operation. Thus, signal path {circle around (9)} of FIG. 8B is formed, whereby the data value stored in main register 420 may be retained or changed. If the selected memory cell has been programmed from storing the data value “10” to storing a data value “00,” latch nodes N3 and N4 of main register 420 are set to a logic low level and a logic high level, respectively. Afterwards, the selected memory cell is program-inhibited during any subsequently executed MSB program loops.

In accordance with the “00” verify read operation described above, even though the selected memory cell may have been programmed to have a threshold voltage greater than the a threshold voltage that corresponds to the data value “00,” if the data stored in main register 420 corresponds to the operation of programming the selected memory cell from storing the data value “11” to storing the data value “01,” the data in main register 420 is retained as program-enable data (i.e., not program-inhibit data). That is, since signal path {circle around (9)} of FIG. 8B is not formed, the data value stored in main register 420 does not change. On the other hand, if the data stored in main register 420 corresponds to the operation of programming the selected memory cell from storing the data value “10” to storing the data value “00,” the data in main register 420 is changed into program-inhibit data when the selected memory cell reaches a threshold voltage corresponding to the data value “00.” That is, signal path {circle around (9)} of FIG. 8B is formed.

The “01” verify read operation is executed following the “00” verify read operation. During the “01” verify read operation, control signal C11 is set to a logic low level and control signal C5 is set to a logic high level, so NMOS transistors 421 and 441 are turned on. Also during the “01,” verify read operation, a verify voltage Vvfy3 (see FIG. 4B) applied to the selected word line and the resulting voltage level variation of the selected bit line is reflected on sense node S0 through signal path {circle around (7)} of FIG. 8B. For example, if the selected memory cell has a threshold voltage lower than verify voltage Vvfy3, the voltage level of sense node S0 decreases toward a ground voltage, so NMOS transistor 442 in common sense circuit 440 is turned (or remains) off. When NMOS transistor 442 is turned off, signal path {circle around (10)} of FIG. 8B is not formed, so the data stored in main register 420 remains program-enable data. On the other hand, if the selected memory cell has a threshold voltage greater than or equal to verify voltage Vvfy3, the voltage level of the selected bit line increases toward a power supply voltage, so NMOS transistor 442 in common sense circuit 440 is turned on. When NMOS transistor 442 is turned on, signal path {circle around (10)} of FIG. 8B is formed, so the data stored in main register 420 is changed into program-inhibit data.

After the “01” verify read operation is executed, data stored in main register 420 is transferred to page buffer decoder circuit 600 through data output circuit 450 through enabling control signal C7. For example, when latch node N3 has a logic low level, NMOS transistor 451 of data output circuit 450 is turned off. Thus, signal line DOL maintains its pre-charged level. On the other hand, when latch node N3 has a logic high level, NMOS transistor 451 is turned on such that signal line DOL is grounded through signal path {circle around (11)} of FIG. 8B. The logic state of signal line DOL is transferred to a well-known pass/fail check circuit through page buffer decoder circuit 600. The pass/fail check circuit determines, based on the data input to the pass/fail check circuit, whether the selected memory cell has been successfully programmed. Based on the judgment result, another MSB program loop is performed or the MSB program operation ends.

FIG. 9A is a circuit diagram illustrating the flow of data through portions of a flash memory device in accordance with the present invention during an MSB read operation, and FIG. 9B shows a read voltage applied to the selected word line during an MSB read operation. In accordance with the present invention, a memory cell may store one of four data values: “11,” “10,” “00,” or “01.” As illustrated in FIG. 9B, the four data values “11,” “10,” “00,” and “01” are assigned, respectively, over four threshold voltage distributions that are arranged in ascending order with regard to voltage level. Accordingly, it is possible to read the MSB data stored in a selected memory cell by determining whether the data value stored in the selected memory cell is in a first or a second data value group, wherein the first data value group comprises the data values “11” and “10,” and the second data value group comprises the data values “00” and “01.” If the data value stored in the selected memory cell is “11” or “10” (i.e., in the first data value group), then the MSB is “1,” and if the data value stored in the selected memory cell is “00” or “01” (i.e., in the second data value group), then the MSB is “0”. An MSB read operation will now be described with reference to FIGS. 3, 9A, and 9B.

During the MSB read operation, a read voltage Vread1 (refer to FIG. 9B) is applied to a word line and the resulting voltage level variation of the selected bit line is reflected on sense node S0 through signal path {circle around (1)} of FIG. 9A. When the selected memory cell has a threshold voltage that is lower than read voltage Vread1, the voltage level of sense node S0 decreases toward a ground voltage, so NMOS transistor 442 in sense circuit 440 is turned (or remains) off. On the other hand, when the selected memory cell has a threshold voltage greater than or equal to read voltage Vread1, the voltage level of sense node S0 increases toward a power supply voltage, so NMOS transistor 442 is turned on. During the MSB read operation, control signal C5 is set to a logic high level and control signal C11 is set to a logic low level. Under the conditions set forth above, NMOS transistors 421 and 441 are turned. If the voltage level of sense node S0 decreases to a ground voltage, signal path {circle around (2)} of FIG. 9A is not formed. However, if the voltage level of sense node S0 increases toward a power supply voltage, signal path {circle around (2)} of FIG. 9A is formed. That is, {cell data of the} [a data value that corresponds to the data value stored in the] selected memory cell is stored in main register 420. Afterwards, data stored in main register 420 is transferred to page buffer decoder circuit 600 through data output circuit 450 through enabling a control signal C7 (see signal path {circle around (3)} of FIG. 9A). MSB data transferred to page buffer decoder circuit 600 is transferred outside of flash memory device 1000 (of FIG. 2) through a data line bus.

FIG. 10A is a circuit diagram illustrating the flow of data through portions of a flash memory device in accordance with the present invention during an LSB read operation, and FIG. 10B shows read voltages applied to the selected word line during an LSB read operation. An LSB read operation, which comprises a first LSB sense operation and a second LSB sense operation, will now be described in detail with reference to FIGS. 3, 10A, and 10B.

During the first LSB sense operation of the LSB read operation, a read voltage Vread2 (refer to FIG. 10B) is applied to the selected word line and the resulting voltage level variation of the selected bit line is reflected on sense node S0 through signal path {circle around (1)} of FIG. 10A. When the selected memory cell has a threshold voltage that is lower than read voltage Vread2, the voltage level of sense node S0 decreases toward a ground voltage; and thus, NMOS transistor 442 in common sense circuit 440 is turned (or remains) off. On the other hand, when the selected memory cell has a threshold voltage that is greater than or equal to read voltage Vread2, the voltage level of sense node S0 increases toward a power supply voltage; and thus, NMOS transistor 442 is turned on. During the first LSB sense operation, control signal C5 is set to a logic high level and control signal C11 is set to a logic low level, so NMOS transistors 421 and 441 are turned on. If the voltage level of sense node S0 decreases toward a ground voltage, signal path {circle around (2)} of FIG. 10A is not formed. If the voltage level of sense node S0 increases toward a power supply voltage, signal path {circle around (2)} of FIG. 10A is formed.

Then, during the second LSB sense operation of the LSB read operation, a read voltage Vread3 (refer to FIG. 10B) is applied to the selected word line and the resulting voltage level variation of the selected bit line is reflected on sense node S0 through signal path {circle around (3)} of FIG. 10A. When the selected memory cell has a threshold voltage that is lower than read voltage Vread3, the voltage level of sense node S0 decreases toward a ground voltage; and thus, NMOS transistor 442 in common sense circuit 440 is turned (or remains) off. On the other hand, when the selected memory cell has a threshold voltage that is greater than or equal to read voltage Vread1, the voltage level of sense node S0 increases toward a power supply voltage; and thus, NMOS transistor 442 is turned on. During the second LSB sense operation, control signal C6 is set to a logic high level and control signal C11 is set to a logic low level, so NMOS transistors 422 and 442 are turned. If the voltage level of sense node S0 decreases toward a ground voltage, signal path {circle around (4)} of FIG. 10A is not formed. If the voltage level of sense node S0 increases toward a power supply voltage, signal path {circle around (4)} of FIG. 10A is formed.

Afterwards, the LSB data stored in main register 420 is transferred to page buffer decoder circuit 600 through data output circuit 450 through enabling control signal C7 (see signal path {circle around (5)} of FIG. 10A). LSB data transferred to page buffer decoder circuit 600 is transferred outside of flash memory device 1000 (of FIG. 2) through a data line bus.

A page buffer circuit of a flash memory device in accordance with the present invention performs program and read functions for multi-bit data, and also performs cache program and page copy-back functions for single-bit data. The cache program and page copy-back operations will be described below.

In the cache program operation, during the execution of the first program operation described above, data to be programmed during the next first program operation is loaded into the cache register.

The cache program operation will now be described in more detail with reference to FIGS. 3 and 11. Program data is first loaded into cache register 410 through signal path {circle around (1)} of FIG. 11, and the data in cache register 410 is then transferred into main register 420 through signal paths {circle around (2)} and {circle around (3)} of FIG. 11. Once program data is transferred to main register 420, the voltage level of the selected bit line is determined in accordance with the data stored in main register 420 through signal path {circle around (4)} of FIG. 11. The operational steps illustrated by signal paths {circle around (1)}, {circle around (2)}, {circle around (3)}, and {circle around (4)} are the same as those described above with reference to FIG. 6, so description thereof is omitted here. Then, a first program operation is performed, wherein the first program operation is the same as the first program operation mentioned previously. Also, as mentioned previously, the first program operation is well known in the art, so a description thereof is omitted here. While the data in main register 420 is programmed, program data corresponding to the data value that will be programmed next is loaded into cache register 410 through signal path {circle around (5)} of FIG. 11. The preceding operational steps are repeated in the manner described above with reference to FIG. 11 until the desired amount of data has been programmed.

In a page copy-back operation, as illustrated in FIG. 12A, a page buffer circuit reads data stored in one page, and then programs that data into another page. Referring to FIG. 12B, which illustrates the flow of data through portions of a flash memory device in accordance with the present invention during a page copy-back operation, and FIG. 3, data read through signal paths {circle around (1)}, and {circle around (2)} of FIG. 12B is stored in main register 420. The data stored in main register 420 is then programmed into another page through signal path {circle around (3)} of FIG. 12B. The operational steps illustrated by signal paths {circle around (1)} and {circle around (3)} of FIG. 12B are the same as those described above with reference to signal paths {circle around (5)} and {circle around (4)} of FIG. 6, respectively, so description thereof is omitted here. Also, the operational step illustrated by signal path {circle around (2)} of FIG. 12B is the same as the operational step described above with reference to signal path {circle around (4)} of FIG. 10A, so a description thereof is omitted here. Alternatively, as illustrated in FIG. 12C, the page copy-back operation may be performed by reading data through signal path {circle around (1)} of FIG. 12C, storing the data in cache register 410 through signal path {circle around (2)} of FIG. 12C, transferring the data stored in cache register 410 to main register 420 through signal paths {circle around (3)} and {circle around (4)} of FIG. 12C, and then programming the data stored in main register 420 into another page. The operational steps illustrated by signal paths {circle around (1)}, {circle around (3)}, {circle around (4)}, and {circle around (5)} of FIG. 12C are the same as those described above with reference to signal paths {circle around (5)}, {circle around (2)}, {circle around (3)}, and {circle around (4)} of FIG. 6, respectively, so description thereof is omitted here. In addition, the operational step illustrated by signal path {circle around (2)} of FIG. 12C is the same as the operational step described above with reference to signal path {circle around (5)} of FIG. 8A, so description thereof is omitted here.

It is possible to update a portion of the data read from one page during a page copy-back operation. That is, as illustrated in FIG. 13A, a page buffer circuit reads data stored in one page, and data to be updated is loaded into the page buffer circuit. Then, data stored in the page buffer circuit is programmed into another page. FIG. 13B illustrates the flow of data through portions of a flash memory device in accordance with the present invention during a page copy-back operation. Referring to FIGS. 3 and 13B, data is first read through signal path {circle around (1)} of FIG. 13B, and then is stored in cache register 410 through signal path {circle around (2)} of FIG. 13B. Data to be updated is then loaded into cache register 410 through signal path {circle around (3)} of FIG. 13B in the same manner as described above with reference to signal path {circle around (1)} of FIG. 6. Then, data in cache register 410 is transferred to main register 420 through signal paths {circle around (4)} and {circle around (5)} of FIG. 13B, and the data stored in main register 420 is then programmed into another page through signal path {circle around (6)} of FIG. 13B. The operational steps that correspond to signal paths {circle around (1)}, {circle around (3)}, {circle around (4)}, {circle around (5)}, and {circle around (6)} of FIG. 13B are the same as those described above with reference to signal paths {circle around (5)}, {circle around (1)}, {circle around (2)},{circle around (3)}, and {circle around (4)} of FIG. 6, respectively, so description thereof is omitted here. In addition, the operational step illustrated by signal path {circle around (2)} of FIG. 13B is the same as the operational step described above with reference to signal path {circle around (5)} of FIG. 8A, so description thereof is omitted here.

The activations of the various control signals within a page buffer is not limited to the exemplary activations described above. For example, it will be clear to one skilled in the art that the activation of various control signals within a page buffer can be changed in accordance with reset states of the latches in registers 410 and 420. Also, it will be clear to one of ordinary skill in the art that single-bit program and read operations may also be performed in a flash memory device comprising a page buffer in accordance with an embodiment of the invention.

As described above, it is possible to perform various operations in a flash memory device comprising a single page buffer structure.

The operations described above are each performed in relation to a single memory cell; however, it will be clear to one of ordinary skill in the art that the operations could be applied to multiple memory cells in various ways.

The invention has been described with reference to exemplary embodiments. However, it will be understood that the scope of the invention is not limited to the disclosed embodiments, but rather is intended to cover various modifications, adaptations, and alternate arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications, adaptations and alternative arrangements. 

1. A flash memory device comprising: a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines; a common node; a sense node connected to a selected bit line; a first register connected to the common node; a second register connected to the common node and the sense node; a common sense circuit connected to the common node, the sense node, and a control node and configured to selectively provide a first voltage to the common node in accordance with a voltage level of the sense node and a voltage level of the control node; a switch configured to provide a second voltage to the control node, wherein the second voltage corresponds to a first data value stored in the first register; and, a pre-charge circuit connected to the control node and configured to pre-charge the control node.
 2. The flash memory device of claim 1, wherein the switch and the pre-charge circuit are both controlled in accordance with a latch control signal.
 3. The flash memory device of claim 1, wherein the common sense circuit comprises: a first transistor comprising a source, a drain connected to the common node, and a gate connected to the control node; and, a second transistor comprising a drain connected to the source of the first transistor, a source connected to a ground voltage, and a gate connected to the sense node.
 4. The flash memory device of claim 3, wherein the common sense circuit further comprises: a third transistor comprising a drain connected to the source of the first transistor, a source connected to a ground voltage, and a gate connected to a data dump control signal.
 5. The flash memory device of claim 1, wherein the first register is configured to store a second data value that corresponds to a voltage level of the common node.
 6. The flash memory device of claim 1, wherein the first register is configured to store program data provided through a page buffer decoder circuit.
 7. The flash memory device of claim 1, wherein the pre-charge circuit comprises: a first PMOS transistor connected between a power supply voltage and the control node, and controlled by a latch control signal.
 8. The flash memory device of claim 7, wherein the switch comprises: a second PMOS transistor connected between the first register and the control node and controlled by an inverted version of the latch control signal; and, an NMOS transistor connected between the first register and the control node and controlled by the latch control signal.
 9. The flash memory device of claim 1, further comprising: a load circuit configured to supply a current to the sense node.
 10. The flash memory device of claim 1, further comprising: a data output circuit configured to output data stored in the second register to a data line via a page buffer decoder circuit.
 11. A flash memory device comprising: an array of memory cells arranged along a plurality word lines and a plurality of bit lines; a bit line select and bias block configured to select a group of bit lines comprising at least one of the plurality of bit lines; and, a page buffer block comprising a plurality of page buffers, each page buffer corresponding to at least one of the plurality of bit lines, wherein each of the page buffers comprises: a common node; a sense node connected to a selected bit line; a first register connected to the common node; a second register connected to the common node and the sense node; and a common sense circuit electrically coupled to the common node, the sense node and the first and second registers, wherein the common sense circuit is adapted to set the first and second registers respectively through the common node in response to a voltage apparent at the sense node and an externally applied control signal.
 12. The flash memory device of claim 11, wherein the common sense circuit comprises: a first transistor comprising a source, a drain connected to the common node, and a gate connected to a control node; and a second transistor comprising a drain connected to the source of the first transistor, a source connected to a ground voltage, and a gate connected to the sense node.
 13. The flash memory device of claim 12, wherein each of the page buffers further comprises: a third connected between a power supply voltage and the control node, and controlled by a latch control signal, and a switch configured to provide a first voltage to the control node, wherein the first voltage corresponds to a first data value stored in the first register.
 14. The flash memory device of claim 13, wherein the switch and the first through third transistors are configured to transfer data from the first register to the second register in accordance with the data dump control signal.
 15. The flash memory device of claim 13, wherein the switch comprises: a fourth transistor connected between the first register and the control node and controlled by the latch control signal; and, a fifth transistor connected between the first register and the control node and controlled by an inverted version of the latch control signal.
 16. The flash memory device of claim 13, wherein the first register comprises: a latch comprising a first latch node and a second latch node; a register switch circuit configured to selectively connect the first latch node to a ground voltage in response to control signals, and configured to selectively connect the second latch node to the ground voltage in response to the control signals; and, an NMOS transistor connected between the common node and the second latch node and controlled by an initial read control signal.
 17. The flash memory device of claim 13, wherein the first register is configured to store a second data value in accordance with a voltage level of the common node.
 18. The flash memory device of claim 13, wherein the first register is configured to store program data provided via a page buffer decoder circuit.
 19. The flash memory device of claim 13, wherein each of the page buffers further comprises: a data output circuit configured to output data stored in the second register to a data line via a page buffer decoder circuit.
 20. The flash memory device of claim 13, wherein the second register is configured to supply a bit line bias voltage to a selected bit line in accordance with data stored in the second register.
 21. The flash memory device of claim 13, wherein the common sense circuit further comprises; a fourth transistor comprising a drain connected to the source of the first transistor, a source connected to a ground voltage, and a gate connected to a data dump control signal. 